rtldoc is a Python package and CLI tool that automatically generates documentation for SystemVerilog-based hardware projects using the Bender package manager. It produces structured documentation with diagrams via Graphviz and integrates with tools like Slang for parsing. Primarily used by digital hardware and EDA engineers to document RTL designs.
In the Developer Tools space, rtldoc takes a focused approach. It focuses on generating documentation for hardware design projects written in SystemVerilog. It is built as an open-source project for hardware engineers. The project is open source (Apache-2.0). rtldoc is available on the command line.
lionnus builds and maintains rtldoc, and it first shipped in 2026. Development happens publicly on GitHub with 1 commit in the last 90 days. Among its 3 catalogued features are RTL Documentation, Graphviz Diagrams, and SystemVerilog Support.
Summary written by a language model from the project’s public pages.
What PulseGate has recorded for this listing
Same category — not a similarity match